One type of digital data communication protocol utilizes data signals with an embedded clock on a single channel. In these protocols, the receiving circuit includes a clock and data recovery CDR circuit which produces a recovered clock, based typically on a local reference clock that has a frequency close to that of the transmit clock. The receiving circuit uses the recovered clock to sample the data on the channel. Phase differences between the recovered clock and the data signal can be detected and used as feedback in the generation of the recovered clock, so that it tracks the transmit clock on each channel as closely as possible.
One limitation on the data rate in communication channels is jitter tolerance. As the data rates increase, and the data sensing windows become smaller, the specifications for maximum allowed jitter for integrated circuits is becoming tighter. In CDR based systems, jitter can arise from a number of sources. For example, variations in the transmit clock due to transmit side circuits typically cause relatively low frequency jitter. Also, power supply noise-induced jitter on the receiver side typically includes higher frequency components. The dithering of the local clock caused by the CDR circuit itself is also a source of jitter. Also, frequency offsets in the data signals can prevent a CDR circuit from achieving a lock condition that can track the timing of the data signals.
During manufacturing, integrated circuits are tested for characteristics such as the data rate at which they can be used reliably in a variety of conditions. One of the conditions that is desirable to test, is tolerance of the receivers on the communication channels to variations in sample times, such as jitter and intentional frequency shifts such as those encountered in spread spectrum systems.
Unfortunately, this type of testing often requires high-precision test equipment to generate a test signal that mimics different jitter conditions. The generation of desired jitter conditions can be imprecise (especially at high signaling rates) and be limited by test equipment precision. In addition, the requirement for high-precision equipment renders it difficult to test manufactured devices outside of a test facility.
Thus, it is desirable to provide systems for determining whether the CDR circuits are able to achieve lock under conditions of stress caused by frequency offsets and various jitter conditions, and for measuring tolerance to different types of timing variations.